1. Field of the Invention
The present invention relates to a semiconductor memory device. In particular, the present invention relates to a semiconductor memory device using a memory cell formed of a ferroelectric material.
2. Description of the Related Art
FIG. 8 and FIG. 9 individually show a circuit diagram and cross-sectional view of a semiconductor memory device using a memory cell formed of a ferroelectric material. As shown is FIG. 8 and FIG. 9, a unit cell U is formed in a manner that source and drain terminals of a cell transistor T are connected to both terminals of a ferroelectric capacitor C. Several unit cells U are connected in series. A cell block CB is composed of several unit cells. The cell block CB is connected to a bit line BL via a select transistor ST. A ferroelectric memory having the foregoing structure is called a TC parallel unit series connection type ferroelectric memory. In the cell block CB, interconnection connected to a termination unit cell U opposite to the select transistor ST is called a plate line PL.
FIG. 10 is a graph showing the relationship between data read voltage and bit line capacitance in ferroelectric memory. As seen from FIG. 10, the bit line capacitance is optimized, and thereby the maximum read voltage is obtained. However, actually manufactured ferroelectric memories have bit line capacitance larger than the optimal value. For this reason, the read voltage is larger than the maximum value. As a result, there is a high possibility that read data is affected by noise.